Analog delay with chorus and vibrato on two 4096-stage bucket brigades, 1979 style

Parts and what they do

Stock values. Tap a part on the schematic to change it.

R52, 10 Ω

Separates the op-amps’ and the NE570’s supply (B) from the rest.

C37, 100 µF electrolytic

Filter cap on B.

R50, 100 kΩ

Lower half of the −7.5 V divider.

R51, 100 kΩ

Upper half of the −7.5 V divider. The op-amps’ inputs work around this line (C).

C36, 1 µF electrolytic

Filters the −7.5 V line.

R1, 2.2 MΩ

Holds the input at 0 V so the jack doesn’t pop.

C1, 100 nF

Input coupling cap. With R2 the corner is about 16 Hz.

R2, 100 kΩ

U1A’s input resistor. It sets the input impedance near 100 kΩ.

U1A, RC4558

Input stage, inverting. Its gain is (R3 + Level) / R2, from about 0.2 to 10 (−13 to +20 dB). Both the dry and the delayed signal come from here, so Level sets how hard the delay side is driven.

R3, 22 kΩ

In series with Level. It sets the lowest gain.

Level, 1 MΩ pot, audio taper

Level, 1 MΩ audio taper as a variable resistor in U1A’s feedback. Turned up, U1A’s gain rises: about 0.3 at 0.2, 1.0 at half, 10 full up. The overload LED (not drawn) is the pedal’s guide for setting it.

C2, 27 pF

Across the feedback. With Level at half it rolls off above about 70 kHz.

C3, 47 µF electrolytic

Couples U1A to the dry line.

R28, 47 kΩ

Holds the dry line at 0 V.

C4, 1.2 nF

Across R4. With R4 and R5 it lifts the treble going into the delay, from about 2.6 kHz (pre-emphasis).

R4, 100 kΩ

Feeds the guitar into U1B.

R5, 100 kΩ

Feeds the repeats into U1B beside the guitar. R4 and R5 make U1B’s + input the mix of the two.

C5, 22 nF

Couples the Feedback wiper into R5. With R5 it cuts the repeats’ lows below about 70 Hz.

U1B, RC4558

Gain 2 into the compressor.

R6, 200 kΩ

U1B’s feedback.

R7, 200 kΩ

With R6, a gain of 2.

C17, 1 µF electrolytic

Keeps U1B at a gain of 1 for DC.

C7, 220 nF

Couples U1B into the compressor.

U6 (1 to 8), NE570 (one half)

NE570 half wired as a compressor, from −15 V (pin 4) to ground (pin 13). The input goes in at pin 6 through the chip’s R3, and the rectifier and gain cell listen to the output through C8. Every 2 dB change at the input is about 1 dB at the output, so quiet parts go into the delay louder.

R9, 68 kΩ

Across the chip’s R3 (20 kΩ), from pin 6 to pin 5. It lowers the input resistor to about 15 kΩ, so the compressor’s level is slightly higher.

R11, 68 kΩ

Half of the compressor’s DC feedback.

R8, 68 kΩ

Other half of the DC feedback.

C9, 10 µF electrolytic

Grounds the middle of R11 and R8 for audio, so they set only the DC.

C8, 4.7 µF electrolytic

Feeds the compressor’s output to its rectifier and gain cell.

C6, 1 µF electrolytic

The compressor’s rectifier cap. With the chip’s 10 kΩ it sets how fast the gain follows the level, about 10 ms.

R10, 24 kΩ

First resistor of the low-pass ahead of the first delay chip.

R12, 51 kΩ

With R10 it divides the signal to about two thirds, which U2A’s gain of 2 makes back.

C10, 2.7 nF

Filter cap to U2A’s output (Sallen-Key).

R13, 16 kΩ

Second filter resistor.

C11, 2.7 nF

Filter cap to ground. A two-pole low-pass near 3.7 kHz with a slight peak, so nothing near the clock gets into the chip.

U2A, RC4558

Filter amp, gain 2.

R14, 33 kΩ

U2A’s feedback.

R15, 33 kΩ

With R14, a gain of 2.

R16, 1 kΩ

With C13, one more pole near 4.8 kHz.

C13, 33 nF

Filter cap after R16.

C14, 1 µF

Non-polar coupling cap into the first delay chip.

R21, 6.8 kΩ

Feeds U7’s gate supply (VGG, pin 8) from −15 V, with VR6 under it.

VR6 Bias, 100 kΩ pot, linear taper

Bias trim for U7. It sets the DC on the chip’s input through R20. At half, assumed, −7.0 V, the middle of the chip’s swing on 15 V.

R20, 82 kΩ

Carries the bias to U7’s input.

U7, MN3005

First MN3005 bucket brigade, 4096 stages, a P-channel chip on −15 V. The delay is 2048 clock periods, 16 to 205 ms. Its two outputs are drawn as one pin. Swing set to 2.5 V for 15 V, assumed. Clock feedthrough isn’t modeled.

R22, 2.4 kΩ

From output 1 (pin 3) to the load.

R23, 2.4 kΩ

From output 2 (pin 4) to the load. The two outputs meet here and the clock steps mostly cancel.

R24, 100 kΩ

Load on U7’s outputs.

C15, 1 µF

Non-polar coupling cap to U2B.

R25, 100 kΩ

U2B’s input resistor.

U2B, RC4558

Inverting stage between the chips, gain (R26 + VR7) / R25. Its + input sits on VR8, so its output carries U8’s bias.

R26, 39 kΩ

In series with the gain trim.

VR7 Gain, 100 kΩ pot, linear taper

Gain trim between the chips, a variable resistor: U2B’s gain from 0.39 to 1.39. At 0.63, assumed, 1.02, which brings the first repeat back at the dry signal’s level, as EHX’s setup asks.

R63, 6.8 kΩ

Feeds U8’s gate supply (VGG, pin 8) from −15 V, with VR8 under it.

VR8 Bias, 100 kΩ pot, linear taper

Bias trim for U8, on U2B’s + input. At half, assumed, −7.0 V on U8’s input.

U8, MN3005

Second MN3005, on the same clock. Together the two chips delay the signal 4096 clock periods, about 33 to 410 ms. Its two outputs are drawn as one pin.

VR10 Bal., 5 kΩ pot, linear taper

Balance trim across U8’s two outputs, so the clock steps cancel. Here both ends are on the one output pin, so at half it’s 1.25 kΩ in series. The clock steps it cancels aren’t modeled.

R27, 100 kΩ

Load on U8’s outputs.

C33, 220 nF

Couples U8 to U3A.

R48, 680 kΩ

U3A’s input resistor.

U3A, RC4558

Inverting stage after the second chip, gain (R47 + VR9) / R48, 0.15 to 0.29.

R47, 100 kΩ

In series with the gain trim.

VR9 Gain, 100 kΩ pot, linear taper

Gain trim after the chips, a variable resistor. With VR7 it sets the delay’s level into the expander.

R46, 16 kΩ

First resistor of the first output filter.

C31, 2.7 nF

Filter cap to U3B’s output (Sallen-Key).

R45, 16 kΩ

Second filter resistor.

C32, 2.7 nF

Filter cap to ground.

U3B, RC4558

Filter amp, gain 2.37. The gain sets the filter’s peak: a two-pole low-pass near 3.7 kHz, steeper than the one before the chips.

R43, 33.2 kΩ

U3B’s feedback.

R44, 24.3 kΩ

With R43, a gain of 2.37.

C30, 4.7 µF electrolytic

Keeps U3B at a gain of 1 for DC.

R42, 470 Ω

With C29, a pole near 7 kHz.

C29, 47 nF

Filter cap after R42.

R41, 15 kΩ

First resistor of the second output filter.

C27, 2.7 nF

Filter cap to U4A’s output.

R40, 16 kΩ

Second filter resistor.

C28, 2.7 nF

Filter cap to ground.

U4A, RC4558

Filter amp, gain 1.38. With the filters before it, the repeats fall off steeply above about 3 kHz.

R38, 15 kΩ

U4A’s feedback.

R39, 39 kΩ

With R38, a gain of 1.38.

C26, 4.7 µF electrolytic

Keeps U4A at a gain of 1 for DC.

C25, 4.7 µF electrolytic

Couples the filtered delay into the expander.

U6 (9 to 16), NE570 (one half)

NE570 half wired as an expander. The rectifier and gain cell take the delayed signal. Every 1 dB at its input is about 2 dB at its output, which undoes the compressor and pushes the delay chips’ hiss down when the signal is quiet.

C23, 1 µF electrolytic

The expander’s rectifier cap, the same as the compressor’s so the two track.

R36, 1.5 MΩ

Across C23. It sets a floor under the expander’s gain, so very quiet signals aren’t cut quite as far.

R37, 11 kΩ

From the expander’s summing node to −15 V. With the chip’s own resistors it sets the output’s DC.

R34, 7.5 kΩ

In series with the chip’s R3 (20 kΩ) in the expander’s feedback. It lowers the expander’s gain slightly.

C22, 470 nF electrolytic

Couples the expander’s output to Feedback.

R35, 1 kΩ

In series with the top of Feedback.

C24, 47 nF

With R35, rolls off the very top of the repeats going back round.

Feedback, 10 kΩ pot, audio taper

How much of the delay goes back through R5 into U1B, so how many repeats. 10 kΩ audio taper. At 0.5 each repeat comes back about 20 dB under the last, at 0.65 about 14, at 0.8 about 7. Full up the repeats grow about 0.9 dB a pass and run away.

R33, 100 kΩ

Puts the expander’s DC level on U4B’s + input.

C21, 1 µF electrolytic

Keeps the signal off U4B’s + input.

R32, 240 kΩ

U4B’s input resistor.

U4B, RC4558

Output stage for the delay, inverting, gain 0.75, rolling off the treble above about 3 kHz (de-emphasis). It undoes U1B’s treble lift on the repeats.

R31, 180 kΩ

U4B’s feedback.

C19, 150 pF

Across the feedback: the de-emphasis, from about 5.9 kHz.

R30, 330 kΩ

With C20, a second step in the de-emphasis.

C20, 120 pF

In series with R30.

C18, 22 µF electrolytic

Couples the delay to Blend.

Blend, 10 kΩ pot, linear taper

Blend, 10 kΩ linear, between the dry line and the delay. Turned up, more delay and less dry. At half both come through.

R29, 150 Ω

In series with the output. On the pedal the footswitch (S1) sits between, with the effect on here.

R53, 13 kΩ

Top of the LFO’s reference divider, from −15 V.

C38, 1 µF electrolytic

Filters the LFO’s reference.

R54, 3.3 kΩ

Between the divider’s two points.

R55, 15 kΩ

Bottom of the divider: the LFO works around this point, about −7.2 V.

U5A, RC4558

Comparator with hysteresis. Its output flips to the other rail each time the triangle reaches a turn, so it puts out a square wave.

R56, 910 kΩ

Positive feedback for the comparator. With R58 it sets the triangle’s turns about 0.8 V each side of the reference.

R58, 120 kΩ

Brings the triangle back to the comparator.

R57, 910 kΩ

The integrator’s input resistor. With the cap S2 picks it sets the rate.

U5B, RC4558

Integrator. The square in makes a triangle out, about 1.7 V peak to peak.

C39, 2.2 µF

Non-polar integrator cap for Chorus: the slow rate.

C40, 470 nF

Integrator cap for Vibrato: about four and a half times as fast.

Chorus-Vibrato, 100 kΩ pot, linear taper

Depth, 100 kΩ linear, from the triangle to the lower point of the LFO’s divider (R53, R54, about −8.8 V). Turned up, more of the triangle reaches the clock and the pitch of the repeats moves further. The triangle sits about 1.6 V above that point, so turning it up also shortens the delay slightly. At 0 the clock holds still.

R59, 7.5 kΩ

With C41, smooths the triangle’s corners on its way to the varactor.

C41, 2.2 µF electrolytic

Smoothing cap. The voltage across it is the varactor’s bias, which moves the clock.

U9, LM311 ramp (stand-in)

The CD4047 clock and its varactor network, as one stand-in. R61 and Delay set the period from about 8 µs (Delay at 0) to 100 µs (full), the sheet’s figures. On the pedal D3, a 1N4001 used for its junction capacitance, hangs on the timing cap (C43, 240 pF) through C42 and C44, 1 nF each. The more reverse bias across it, the less capacitance and the faster the clock. Here the bias is the voltage across C41: each volt shortens the period by about 6 to 7 %, from a simulation of the network.

R61, 5.6 kΩ

In series with Delay. It sets the shortest delay.

Delay, 100 kΩ pot, linear taper

Delay, 100 kΩ linear as a variable resistor. Turned up, the clock slows and the delay gets longer, in a straight line: about 33 ms at 0, 150 ms at 0.3, 220 ms at half, 410 ms full up.

About this version

As drawn

From a 24 V AC adapter through a 15 V regulator to −15 V. Ground is the most positive point, and every chip runs from −15 V to 0 V. The audio works around the −7.5 V line from R50 and R51.